1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device having a dual damascene line structure and a method for fabricating the same.
2. Description of the Related Art
A damascene or inlay technique is an old technique for ornamenting craftworks. In this technique, various patterns are engraved on the surface of metal, ceramics or wood, and then a different material such as gold, silver or mother-of-pearl is inserted into the engraved portion.
Such a damascene technique has lately attracted attention as a new method of forming a metal line during the fabrication of semiconductor devices. In particular, since IBM Corporation announced that they applied a copper wiring process using a dual damascene technique to the fabrication of semiconductor devices in 1997, a variety of research has been carried out on the copper wiring process using the damascene technique focusing on logic devices.
Generally, it is difficult to dry-etch a copper line since the vapor pressure of by-products is low during a dry etching process, and the copper line is especially subject to corrosion such that it is difficult to use the copper line for a metal line in a semiconductor device.
However, the formation of a copper line becomes possible by using the damascene technique and a chemical mechanical polishing (CMP) process, instead of using dry-etching. Usually, a copper line has lower resistance than other existing metal lines and excellent electro-migration properties. In addition, a copper line allows the number of steps of forming a metal line in a semiconductor device to be reduced so that the fabrication cost can be reduced.
FIGS. 1 and 2 are sectional views illustrating conventional methods of forming a dual damascene line in a semiconductor device.
Referring to FIG. 1, a first conductive pattern 30 is formed on a semiconductor substrate 10, and then a first interlayer insulation layer 20 is formed. A second interlayer insulation layer 40 is formed on the first interlayer insulation layer 20. Subsequently, photolithography is performed to form a second interlayer insulation layer 40 pattern exposing a portion of the first interlayer insulation layer 20. Finally, a photoresist pattern 50 is formed on the semiconductor substrate 10 having the second interlayer insulation layer 40 pattern, and then an etching process is performed, thereby forming via contact holes 60 exposing the first conductive pattern 30.
However, in the conventional method of forming a damascene line in a semiconductor device described above, when an aspect ratio is large during dry etching for forming a via contact hole, the bottom of the via contact hole is not completely opened (70) due to the influence of a resulting etching slope and by-products. This problem becomes more severe as the integration density of semiconductor devices increases. To solve this problem, an etching stopper layer is provided between the first interlayer insulation layer and the second interlayer insulation layer.
Referring to FIG. 2, a first conductive pattern 31, a first interlayer insulation layer 21, a second interlayer insulation layer 41 and a photoresist pattern 51 are formed on a semiconductor substrate 11 in the same manner as used in FIG. 1. An etching stopper 35 is further formed between the first interlayer insulation layer 21 and the second interlayer insulation layer 41 using a silicon nitride (SiN) layer.
This method solves the problem of the bottom of a via contact hole 61 not being opened by performing over-etching using the etching stopper 35; however, a nitride layer, i.e., the etching stopper 35, having a high dielectric constant should be formed between the interlayer insulation layers. When a material having a high dielectric constant is used between the interlayer insulation layers, parasitic capacitance in the interlayer insulation layers increases, thereby increasing RC delay during operation of the semiconductor device.
To address the above limitations, it is an object of the present invention to provide a semiconductor device having a dual damascene line structure that solves the aforementioned problem of the bottom of a via contact hole not being opened by using an etching stopper, and for reducing the parasitic capacitance of an interlayer insulation layer.
It is another object of the present invention to provide a method for fabricating a semiconductor device having the dual damascene line structure.
Accordingly, to achieve the first object of the invention, there is provided a semiconductor device having a dual damascene line structure. The semiconductor device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a first interlayer insulation layer covering the top of the first conductive pattern, an etching stopper pattern locally formed on the first interlayer insulation layer, a via contact plug formed within the first interlayer insulation layer in an area where the etching stopper pattern is formed such that the via contact plug is connected to the first conductive pattern, a second interlayer insulation layer formed on the etching stopper pattern, and a metal contact plug formed within the second interlayer insulation layer in an area where the etching stopper pattern is formed, wherein a portion of the etching stopper pattern is etched, and thus the metal contact plug is connected to the via contact plug.
The area of the locally formed etching stopper pattern is preferably wider than the area of the bottom of the metal contact plug.
To achieve the second object of the invention, in one embodiment, there is provided a method for fabricating a semiconductor device having a dual damascene line structure. In the method, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern has been formed. An etching stopper is formed on the first interlayer insulation layer. An etching stopper pattern is formed by patterning the etching stopper. A second interlayer insulation layer is deposited on the semiconductor substrate on which the etching stopper pattern has been formed. The second interlayer insulation layer is patterned, thereby forming a first metal trench exposing the etching stopper pattern and a second metal trench where, as well as the second interlayer insulation layer, a portion of the first interlayer insulation layer is etched. Photolithography is performed on the semiconductor substrate, thereby forming a via contact hole exposing the first conductive pattern in an area corresponding to the first metal trench. A second conductive layer is formed to cover the surface of the semiconductor substrate so that the second conductive layer fills the first metal trench, the second metal trench and the via contact hole. The second conductive layer may be planarized using a chemical mechanical polishing method.
In another embodiment, there is provided a method for fabricating a semiconductor device having a dual damascene line structure. In this method, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern has been formed. An etching stopper is formed on the first interlayer insulation layer. An etching stopper pattern is formed by patterning the etching stopper. A second interlayer insulation layer is deposited on the semiconductor substrate on which the etching stopper pattern has been formed. Photolithography is performed on the semiconductor substrate, thereby forming a via contact hole exposing the first conductive pattern. The second interlayer insulation layer is patterned, thereby forming a first metal trench exposing the etching stopper pattern and a second metal trench where, as well as the second interlayer insulation layer, a portion of the first interlayer insulation layer is etched. A second conductive layer is formed to cover the surface of the semiconductor substrate so that the second conductive layer fills the first metal trench, the second metal trench and the via contact hole. The second conductive layer is optionally planarized by a chemical mechanical polishing method.
In still another embodiment, there is provided a method for fabricating a semiconductor device having a dual damascene line structure. In this method, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern has been formed. An etching stopper is formed on the first interlayer insulation layer. First etching stopper patterns are formed by patterning the etching stopper. Photolithography is performed on one of the first etching stopper patterns, thereby forming a second etching stopper pattern allowing a via contact hole to be formed in a self-aligning manner in a later step. A second interlayer insulation layer is deposited on the semiconductor substrate on which the second etching stopper pattern has been formed. Photolithography is performed on the second interlayer insulation layer, thereby forming a first metal trench exposing the second etching stopper pattern and thus forming a self-aligned via contact hole exposing the first conductive pattern, and forming a second metal trench where etching is stopped by another first etching stopper pattern. A second conductive layer is formed to cover the surface of the semiconductor substrate so that the second conductive layer fills the first metal trench, the second metal trench and the via contact hole. The second conductive layer is optionally planarized by a chemical mechanical polishing method.
The second conductive layer is preferably formed of copper. The etching stopper may be formed of a material having a lower etching rate than the first interlayer insulation layer and is preferably formed of a material selected from the group consisting of SiN, SiC and SiO2. The etching stopper pattern may be wider than the first metal trench.
The method preferably further includes the step of forming a layer for improving adhesion or preventing diffusion in the first metal trench, the second metal trench and the via contact hole, before depositing the second conductive layer.
According to the present invention, by locally using an etching stopper pattern in a particular region, the problem of the bottom of a via contact hole being partially opened, or blocked, following its formation, through etching, is solved. In addition, an increase in the dielectric constant of an interlayer insulation layer is restrained due to localized formation, thereby minimizing increase in the parasitic capacitance of the interlayer insulation layer.